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SUMMIT
MICROELECTRONICS, Inc. Dual 10-bit Nonvolatile DAC In-system Programmable Analog
FEATURES * Two 10-bit Nonvolatile DACs - INL 1LSB - DNL: 1LSB * Programmable Configuration * Programmable Power-on Reset Options - Recall Full Scale Value - Recall Zero Scale Value - Recall Mid-Scale Value - Recall NV Register Value * Tandem or Independent Operation of DACs * Power-down mode (short VOUT to gnd)
SMP9210 SMP9211 SMP9212
ISPaTM
OVERVIEW The SMP9210 is a serial input, voltage output, dual 10-bit digital to analog converter. It can operate from a single +2.7V to +5.5V supply. Internal precision buffers swing rail-to-rail with an input reference range from ground to the positive supply. The SMP9210 integrates two 10-bit DACs and their associated circuits that include; an enhanced unity gain operational amplifier output, a 10-bit volatile data latch, a 10-bit nonvolatile data register and an industry standard 2-wire serial interface.
BLOCK DIAGRAM
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MICROELECTRONICS, Inc.
SMP9210 SMP9211 SMP9212
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SMP9210 Signal A2 A1 A0 VREFH2 VREFL2 VOUT2 Gnd CS VOUT1 VREFL1 SCL VREFH1 VDD SDA SMP9211 Signal A2 A1 A0 VREFH2 VREFL2 VOUT2 Gnd MUTE VOUT1 VREFL1 SCL VREFH1 VDD SDA SMP9212 Signal A2 A1 A0 VREFH2 VREFL2 VOUT2 Gnd VREF VOUT1 VREFL1 SCL VREFH1 VDD SDA
MICROELECTRONICS, Inc.
SMP9210 SMP9211 SMP9212
Pin 1 2 3 4 5 6 7 8 10 11 12 13 14
Function Address Pin A2 Address Pin A1 Address Pin A0 DAC2 VREFH Input DAC2 VREFL Input DAC2 VOUT Ground Chip Select DAC1 VOUT DAC1 VREFL Input Serial Clock Input DAC1 VREFH Input Supply Voltage Bi-directional Serial Data
Pin 1 2 3 4 5 6 7 8 10 11 12 13 14
Function Address Pin A2 Address Pin A1 Address Pin A0 DAC2 VREFH Input DAC2 VREFL Input DAC2 VOUT Ground Mute Input DAC1 VOUT DAC1 VREFL Input Serial Clock Input DAC1 VREFH Input Supply Voltage Bi-directional Serial Data
Pin 1 2 3 4 5 6 7 8 10 11 12 13 14
Function Address Pin A2 Address Pin A1 Address Pin A0 DAC2 VREFH Input DAC2 VREFL Input DAC2 VOUT Ground Reference Voltage Output DAC1 VOUT DAC1 VREFL Input Serial Clock Input DAC1 VREFH Input Supply Voltage Bi-directional Serial Data
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PIN DESCRIPTION GND is the device ground pin. VOUT is the voltage output of the DACs. It is buffered by a unity-gain follower that can slew up to 1V/s. VREFL is the lower of the voltage reference inputs. VREFL must be equal to or greater than ground and less than VREFH. VREFH is the higher of the voltage reference inputs. VREFH must be equal to or less than VCC and greater than VREFL. A0, A1 and A2 are the address inputs to the SMP9210 serial interface logic. Biasing the address inputs will determine the device's bus address that is contained within the serial data stream when communication over the serial bus. SCL is the serial interface clock. It is used to clock data into and out of the SMP9210. When writing to the device, data must remain stable while SCL is HIGH. When reading, data is clocked out of the SMP9210 on the falling edge of SCL. SDA is a bi-directional pin used to transfer data into and out of the SMP9210. Pin 8 is a multifunction pin and is in-system programmable by the customer or it can be configured by Summit prior to shipment. It can function as Chip Select input (VIH = selected), a MUTE input (VIH = mute) or as a Vref output (1.25V). Device Operation The SMP9210 has two, 10-bit, digital to analog converters that are comprised of a resistor network that converts 10-bit digital inputs into equivalent analog output voltages in proportion to the applied reference voltages. The voltage differential between the VREFL and VREFH inputs sets the full-scale output voltage for its respective DAC. Each DAC has a 10-bit volatile register that holds the digital value decoded by the DAC into an analog voltage output. The register can be written directly via the serial interface, commanded to load the zero scale value, full scale value or mid-scale value or recall a preset value stored in a nonvolatile register. Each DAC has a 10-bit nonvolatile register that can hold a 'set-and-forget' value that can be recalled whenever the device is powered-on. The SMP9210 also has a nonvolatile configuration register that is accessible over the 2wire bus. The configuration register is used to
SMP9210 SMP9211 SMP9212
select the device type identifier, the function of pin 8 and the DAC power-on state. Accessing the DACs The SMP9210 uses the industry standard 2-wire serial protocol. The bus is designed for two-way, two-line serial communication between different integrated circuits. The two lines are the SCL (serial clock) and SDA (serial data) and both lines must be tied to the positive supply through a pull-up resistor.. The protocol defines devices as being either masters or slaves, the SMP9210 will always be a slave in that it does not initiate any communications or provide a clock output. Data transfers are initiated when a master issues a 'start' condition, which is a high to low transition on SDA while SCL is high. The start is immediately followed by an eight bit transmission: bits 7:1 comprise the device type identifier and bus device bus address; bit 0 is the read/write bit indicating the action to follow. If the intended device receives the byte and recognizes its address it will return an acknowledge during the 9th clock cycle. Some data transfers will be concluded with a 'stop' condition, which is a low to high transition on SDA while SCL is high. Note: a stop condition must be performed for all nonvolatile write operations. Addressing Convention S T A A 0 1 0 1 2 R T
A 1
A 0
R/ W
A C K
The DAC device type identifier default is 0101[b]. In order to accommodate more than eight devices on a single bus, the device type identifier can by modified by the end user by writing to the configuration registers. The command structure is illustrated in Table 1. Of special note is the ability to write individually to the two DACs or write to them in tandem. The first three commands are three bytes in length and can either be volatile or nonvolatile. The 'Zero' commands load all zeroes into the DAC registers forcing the VOUT to VREFL. The 3F commands load all ones into the DAC registers, forcing VOUT to VREFH. The Recall commands, write the nonvolatile register value into the DAC registers. The PD commands connect VOUT to GND. These four commands are all two bytes; the device
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Table 1. Command Structure. MSB 7 6 5 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0 0 0 LSB 0 D8 D8 D8 0 1 1 0 1 1 0 1 1 0 1 1
SMP9210 SMP9211 SMP9212
Command Write DAC1 Write DAC2 Write Both DACS ZeroDAC1 ZeroDAC2 ZeroBOTH 3FDAC1 3FDAC2 3FBOTH RecallDAC1 RecallDAC2 RecallBoth PDDAC1 PDDAC2 PDBOTH Function Write 10-bit value to DAC1 Write 10-bit value to DAC2 Write the same 10-bit value to DAC1 and DAC2 Set DAC1 to Zero Scale (VREFL) Set DAC2 to Zero Scale (VREFL) Set DAC1 & DAC2 to Zero Scale (VREFL) Set DAC1 to Full Scale (VREFL) Set DAC2 to Full Scale (VREFL) Set DAC1 & DAC2 to Full Scale (VREFL) Recall E to DAC1 Recall E to DAC2 Recall E to Both DACs Power Down DAC1 (VOUT to GND) Power Down DAC2 (VOUT to GND) Power Down Both DACs (VOUT to GND)
2 2 2
3 dc dc dc 1 1 1 1 1 1 dc dc dc dc dc dc
2 dc dc dc 1 1 1 1 1 1 dc dc dc dc dc dc
1 D9 D9 D9 1 0 1 1 0 1 1 0 1 1 0 1
*dc = don't care
type/address byte followed by the command byte. They are will be enforced with or without a stop being issued and the new register value is never stored in the nonvolatile register. Writing a value to a DAC can either be a write to the DAC register only or a combined write to both the DAC Register and its nonvolatile register. They are identical with the one exception being the register write does not entail issuing a stop condition; whereas, the nonvolatile write operation is concluded with a stop. The sequence is to issue a start, followed by the device type and bus address, with the read/write bit
Writing to DACs Data Sequence (Volatile Write) S A t A A A C 0 1 0 1 0 1 0 0 1 a 2 1 0 K r t Device Type and Bus Address W Command Writing to DACs Data Sequence (Nonvolatile Write) S t A A A A 0 1 0 1 0 1 0 C a 2 1 0 r K t Command Sequence (example command shown 3FDAC1) S t A A A A 0 1 0 1 0 1 C a 2 1 0 r K t Device Type and Bus Address W
set to zero. The SMP9210 will respond with an acknowledge and the master will then issue the command and follow-on data. In the example below the write is to DAC1, where the command = 1001[b]; the dc bits are don't care, D9 and D8 are the MSBs of the DAC value being written. The SMP9210 will then respond with an acknowledge followed by the master writing the last eight bits. In the first example shown, no stop is generated after the SMP9210 acknowledge; therefore, the write is only to the register. In the second example the SMP9210 acknowledge is followed by a stop; therefore, the data is written to both the DAC register and to the nonvolatile register.
d c
d c
D 9
D 8
A C K
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
A C K
0
1
d c
d c
D 9
D 8
A C K
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
A C K
S t o p
1
1
0
1
1
1
0
A C K
Command
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MICROELECTRONICS, Inc.
SMP9210 SMP9211 SMP9212
The third example illustrates the data sequence for a two-byte command. Special Configurations The SMP9210 can be configured by the end user or by Summit prior to shipment. There is one configuration register and it is accessed through the serial interface using 1001[b] as the device type address. The register is shown below. LSB 10 PL OO RC 0K x 0 Config Register Accessible x x x x x x x 1 Config Register Locked x x x x x 0 0 Power-on Recall all 0's x x x x x 0 1 Power-on Recall all 1's x x x x x 1 0 Power-on Recall Mid Scale x x x x x 1 1 Power-on Recall NVRegister x x x x 0 VOUT = Low Z on Power-Down x x x x 1 VOUT = High Z on Power-Down A A A A Programmable DAC Device Type Address 2 P AAAAo O r 3210HR Z1 xxxxxx 4 3 L Bit 0 - When bit 0 is written as a 1 the configuration register will be locked and it will become inaccessible for reading and writing. Bits 2:1 are use to select the power-on recall value to be loaded into the DAC registers. Bit 3 selects the power down option for the VOUT pins. Bits 7:4 can be used to program unique DAC device type identifiers. When the default 0101 is used the number of SMP9210's allowed on a single bus is limited to eight. This can be expanded infinitely if the CS input is also used. The only drawback is the decoding or use of port pins to drive the CS inputs. If we assume no other devices on the bus and that each DAC device type address is utilized, then the end user can effectively have 256 individually addressable devices on a single bus. Now, combining this capability with the CS pin a microC can enable blocks of 256 SMP9210's vs blocks of 8. MSB 765
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MICROELECTRONICS, Inc.
SMP9210 SMP9211 SMP9212
DAC Analog Characteristics
Symbol Parameter Static Performance N Resolution INL Relative Accuracy DNL Differential Nonlinearity VZSE Zero Scale Error VFS Full Scale Voltage TCV Full-Scale Tempco MATCHING PERFORMANCE Linearity Matching Error ANALOG OUTPUT IOUT Output Current LDREG Load Regualtion @ Halfscale CL Capacitive Load Condition Min. 10 -1.0 -1 0 Type. Max Units Bits LSB LSB mV V ppm LSB +/-5 3 mA LSB pF kHZ % dB dB VCC VCC-? 100 100 5.5 V V A A V
GUARANTEED MONOTONIC Data = 000H Data = 3FFH
+/-0.5 +/-0.5
+1.0 +1 5 VrefH
=/-15 +/-1 Data = 200H, Vout ,3LSB RL = 1K to infinity, Data = 200H No Oscillation R = 10K VA=1Vrms ,f=1KHz, f = 1KHz VIN = 100mV p-p on VrefH
1 500 100 0.08 -60 -60
Dynamic characteristics
BW_10K THD Bandwidth -3dB Total Harmonic Distortion Channel to Channel Isolation Digital Cross Talk
Reference Voltages
VrefH VrefL Power ISY Iref VSY VrefH > VrefL VrefL < VrefH VDD Supply Current Reference Voltage Current Supply Voltage VDD = +5V, excludes Iref 2.7 Gnd+? Gnd
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SMP9210 SMP9211 SMP9212
Symbol IDD
Parameter Power Supply Current Standby or Quiescent Power Down
Condition VDD = 5.5V VDD = 2.7V Excluding Current VDD = 5.5V Through DACs VDD = 2.7V Total Current VDD = 5.5V Including DAC VDD = 2.7V NV Write
Min.
Typ.
Max.
Units mA A
VDD VIH VIL VOL ILI ILO WEND tDR
Supply Voltage SDA, SCL SDA, SCL SDA Input Leakage Output Leakage Write Endurance Data Retention
2.7
5.5 0.7xVDD 0.3xVDD 0.4 10
V V V V mA NVStores Years
IOL = 3mA VIN = 0 to VDD VOUT = 0 to VDD Number of NV Store Operations NVData Retention
1x106 100
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MICROELECTRONICS, Inc.
SMP9210 SMP9211 SMP9212
AC Operating Characteristics (Over Recommended Operating Conditions)
2.7V to 5.5V
Symbol
fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR
Parameter
SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condtion Hold Time Stop Condition Setup Time Clock Edge to Valid Output Data Out Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Filter SCL & SDA Write Cycle Time
Conditions
Min.
0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3
Max.
100
Units
KHz s s s s s s s s ns ns ns ns ns ms
Before New Transmission
SCL low to Valid SDA (cycle n) SCL low (cycle n+1) to SDA change
3.5 1000 300
250 0 Noise Suppression 100 5
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SMP9210 SMP9211 SMP9212
Ordering Information
SMP9210S SMP9211S SMP9212S 14 lead SOIC 14 lead SOIC 14 lead SOIC
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